The present invention relates to semiconductor devices and processing, and more particularly to a structure and method of fabricating a vertically oriented transistor in a silicon-on-insulator layer, the transistor having a body contact.
Speed is a key aspect of operational performance of integrated circuits. In recent years, enhanced fabrication techniques including silicon-on-insulator (SOI) technology have been introduced. SOI technology is becoming increasingly important since it assists in lowering the capacitance of transistors, enabling greater switching speeds. When field effect transistors (“FETs”) are formed in bulk substrates, the junction between the “body” of the transistor (i.e., the portion of the transistor including the transistor channel that is disposed immediately adjacent to the gate dielectric) and the semiconductor material adjacent to the body results in significant capacitance. In SOI substrates, active devices such as field effect transistors (FETs) are formed in a relatively thin layer of semiconductor material (Si) overlying a buried layer of insulating material such as a buried oxide (BOX). SOI technology eliminates the junction capacitance by electrically isolating the body of the transistor from the bulk region of the semiconductor substrate. The BOX layer, the gate dielectric, the source and drain regions, and sometimes additional isolations such as shallow trench isolation (STI) regions electrically isolate the body of the SOI FET.
The electrically isolated body of a transistor formed in an SOI substrate is known as a “floating body” because the body floats at a potential which varies according to various conditions in which the transistor is operated, wherein such potential is usually not known in advance. In consequence, the threshold voltage VT of the transistor is subject to variation, also to an extent that is usually not known in advance. The threshold voltage VT is the voltage at which a FET transitions from an ‘off’ state to an ‘on’ state. FETs are fabricated as either n-channel type FETs (NFETs) or p-channel type FETs (PFETs). Whether the FET is a PFET or an NFET, the floating body of a FET constructed in an SOI substrate may cause the threshold voltage of the FET to vary somewhat over time.
While such variations in the threshold voltage are usually tolerable when the FET is used in a digital switching element such as an inverter or logic gate, FETs used in many applications, such as passgates of DRAM cells need to have a stable threshold voltage.
In a particular example, the floating body may cause the threshold voltage of the NFET to increase, causing the NFET to switch on late for rising signal transitions and early in the case of falling signal transitions. When such NFET is used as the passgate of a DRAM storage cell, the late switching NFET can weaken the signal being stored to the storage cell during writing, as well as weaken the output signal of the storage cell during reading.
In another example, the floating body may cause the threshold voltage of the NFET to decrease. When such NFET used in a storage cell of a DRAM is turned off, the gate of the NFET must be maintained at a voltage which is lower than before to keep leakage current acceptably low. For example, the gate voltage can be maintained at a negative value when the NFET is turned off.
A body contact is an electrically conductive contact made to the body of the transistor to provide, inter alia, a path for the flow of charge carriers to and from the transistor body. A proper body contact can eliminate floating body problems by maintaining the transistor body at a constant potential. DRAM cells can include planar, vertical or hybrid transistors, the hybrid transistors being similar to both planar and vertical transistors. U.S. Pat. No. 5,606,188 to Bronner et al. and U.S. Pat. No. 6,429,477 to Mandelman et al. describe DRAM cells in which a body contact is provided to a planar SOI FET.
In a particular type of DRAM storage cell array, FETs used as passgates have conduction channels which are oriented in a vertical direction along a sidewall of a deep trench, the deep trench extending between an upper surface of the SOI region, through the BOX layer and into the bulk region of the substrate. Heretofore, such FETs, referred to as “vertical FETs”, disposed in SOI substrates have not been fabricated to have body contacts. Because vertical FETs in SOI substrates according to the prior art do not have body contacts, they suffer from the aforementioned floating body problems.